Basilisk

Enlarged view: Basilisk
Basilisk, 2024

Application: Pulp
Technology: 130
Manufacturer: IHP
Type: Research
Package: QFN88
Dimensions: 6264μm x 5498μm
Gates: 3 MGE
Voltage: 1.2 V
Clock: 60 MHz

Design: Basilisk details: IIS Chip Gallery
The Basilisk chip prototype, based on the Cheshire SoC architecture, was taped out using the open-PDK IHP130 technology as well as open-source EDA tools. The Cheshire SoC will be leveraged to integrate the newly developed IPs in future test chips.

Design team: Philippe Sauter, Thomas Benz, Paul Scheffler, Beat Muheim, Zerun Jiang, Frank K. Gurkaynak, Luca Benini

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