HEEPatia

Features: HEEPatia implements a dual-core X-HEEP platform, integrating:

• CV32E40P core
• CV32E40PX core extended with the Coprosit coprocessing unit for posit arithmetic

The system contains 608 kB of on-chip memory, comprising:

• 352 kB of SRAM shared across the MCU and IP blocks
• 256 kB of Gain-Cell Random Access Memory (GC-RAM)

The chip is implemented using a mixture of LVT (Low-Voltage Threshold) and SVT (Standard-Voltage Threshold) standard cells to explore performance-power trade-offs in advanced CMOS technology.

Design: Beyond its dual-core MCU platform, HEEPatia integrates multiple heterogeneous accelerators designed to improve performance and energy efficiency for edge-AI workloads.

These include:

• Two Carus near-memory computing accelerators
• The DISCO (DomaIn-specific System-technology CO-design) CGRA, based on the VWR2A architecture

Application: HEEPatia serves as a research platform for evaluating performance, power, and area (PPA) trade-offs across different hardware IP blocks within a modern 16 nm technology node.

By combining advanced IP blocks within a unified X-HEEP framework, HEEPatia provides a flexible testbed for future embedded and edge computing research.