HEEPnosis

Features:  The chip implements X-HEEP configured with a CV32E2 CPU and integrates 128 kB of on-chip memory, organized into four 32 kB banks (two contiguous banks and two interleaved banks). 

The peripheral set includes: two DMA controllers, SPI interface, GPIOs, UART, and JTAG.

Clock generation is provided by an FLL (Frequency Locked Loop) derived from the PULP project.

HEEPnosis integrates multiple near-memory and experimental hardware components, including: Caesar near-memory macro, Maxwell near-memory macro, and Wukong peripheral.

Design: HEEPnosis is fabricated in GF 22 nm FDX technology, using a mix of:

• LVT (Low-Voltage Threshold) cells
• HVT (High-Voltage Threshold) cells
• UHVT (Ultra-High-Voltage Threshold) cells

Application: HEEPnosis serves as a validation platform for:

• Functionality and efficiency of full-custom blocks designed using logic suppression techniques
• Performance of integrated near-memory macros

As testing is currently ongoing, no published silicon measurement results are available yet.