An Infinite-Loop CMOS-Compatible Isolator Enabled True VSWR-Resilient Power Amplifier for 6G FR3 in Massive MIMO and Phased-Array Systems

Application: Robust cm-wave PA for large-scale phased arrays and massive-MIMO systems where antenna-active-impedance variations induce severe VSWR and reverse intermodulation (RIMD). The architecture targets FR3 (Ku-band ~10-13 GHz) arrays in SATCOM/5G/6G, maintaining output power, efficiency, and linearity under dynamic load mismatch. 

Short Description: A balanced stacked PA with a time-varying output matching network that forms an indirect infinite-loop trap isolator using non-reciprocal phase shifters (NRPS) and hybrid couplers. The loop suppresses backward reflections while relaxing NRPS linearity demands: with 3db NRSP insertion loss, the isolator adds only ≈0.5 dB forward loss and achieves ideal reverse isolation. Fabricated in 22nm CMOS SOI, the PA shows 13.8 dB peak S21 at 11.7 GHz (3 dB BW: 10.5-13 GHz) and S22 < -15 dB from 8-15 GHz. Under 50 Ω, it achieves Psat=23.9 dBm, OP1dB=23.3 dBm, and peak PAE=30.6% (28% incl. clock). Across 3:1/2:1 VSWR contours and 10.2/10.8/11.1/11.4/12 GHz, IP1dB variation stays within ±0.43 dB and OP1dB within ±0.71 dB. With a 400 MHz 64‑QAM at 11.1 GHz, it delivers Pavg=18.69 dBm and PAEavg=19.53%. RIMD testing with a –6 dBc reverse tone (≈3:1 VSWR) yields third‑order RIMD better than –35.5 dBc at 11.1 GHz. The Chip occupies a core/total area of  3/3.75 mm². 

Design Team: CSEM

Paper: M. Ghorbanpoor, M. Eleraky, K. Manetakis, P. Nussbaum and H. Wang, "external page 33.2 An Infinite-Loop CMOS-Compatible Isolator Enabled True VSWR-Resilient Power Amplifier for 6G FR3 in Massive MIMO and Phased-Array Systems," 2026 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2026, pp. 564-566, doi: 10.1109/ISSCC49663.2026.11409051.