Paper on "Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes"

The widespread adoption of data-centric algorithms, particularly Artificial Intelligence (AI) and Machine Learning (ML), has exposed the limitations of centralized processing infrastructures, driving a shift towards edge computing. This necessitates stringent constraints on energy efficiency, which traditional von Neumann architectures struggle to meet. The Compute-In-Memory (CIM) paradigm has emerged as a better candidate due to its efficient exploitation of the available memory bandwidth. However, existing CIM solutions require a high implementation effort and lack flexibility from a software integra- tion standpoint. This work proposes a novel, software-friendly, general-purpose, and low-integration-effort Near-Memory Com- puting (NMC) approach, paving the way for the adoption of CIM- based systems in the next generation of edge computing nodes. Two architectural variants, NM-Caesar and NM-Carus, are proposed and characterized to target different trade-offs in area efficiency, performance, and flexibility, covering a wide range of embedded microcontrollers. Post-layout simulations show up to 28.0 × and 53.9 × lower execution time and 25.0 × and 35.6 × higher energy efficiency at system level, respectively, compared to the execution of the same tasks on a state-of-the-art RISC-V CPU (RV32IMC). NM-Carus achieves a peak energy efficiency of 306.7GOPS/W in 8-bit matrix multiplications, surpassing recent state-of-the-art in- and near-memory circuits.

Paper: 
Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza, "Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes", to appear in external page IEEE Transactions on Emerging Topics in Computing.  [Download Preprint] (PDF, 5.3 MB)