Six papers from ETH Zurich accepted at ESSERC 2025

We are very pleased to announce we have six papers accepted at the upcoming external page ESSERC 2025 taking place in Munich, Germany, September 8-11.
 

Prof. Hua Wang (SwissChips WP4 Lead):

• Edward Liu, Filippo Svelto, and Hua Wang, “A 24 GHz Compact 3:1 VSWR-Resilient Power Amplifier with a Reconfigurable Output Matching Network and Integrated Power Sensors”
  
  
• Puneet Singh, Peter Baumgartner, Hui Zhang, Yuqi Liu, Hua Wang, and Vadim Issakov, “Two 5.6 mW Over-Neutralized 120 GHz Low-Noise Amplifiers in 14 nm FinFET CMOS”

Prof. Luca Benini (SwissChips WP2 Lead): 

• Yichao Zhang, Marco Bertuletti, Sergio Mazzola, Samuel Riedel, and Luca Benini, “A 410 GFLOP/s, 64 RISC-V Cores, 204.8 GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-Ran”

Prof. Christoph Studer (SwissChips Director and WP9 Lead):

• Jonas Elmiger, Fabian Stuber, Oscar Castañeda, Gian Marti, and Christoph Studer, “A 0.32 mm2 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection"  [Read more]
  
  
• Flurin Arquint, Oscar Castañeda, Gian Marti, and Christoph Studer, “A Jammer-Resilient 2.87 mm2 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm” [Read more]
  
  
• Darja Nonaca, Jérémy Guichemerre, Reinhard Wiesmayr, Engin Tunali, and Christoph Studer, “A 14 ns-Latency 9 Gb/s 0.44 mm2 62 pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX" [Read more]