SwissChips PhD students at CSEM to present three papers at ISCAS 2025
As part of SwissChips, PhD students working at CSEM will present three research papers at the IEEE International Symposium on Circuits and Systems (ISCAS) 2025. The papers span neuromorphic sensing, biomedical interfaces, and reference generation, reflecting ongoing efforts to advance the state of the art in analog and mixed-signal design.
An Event-Based Line Sensor with Configurable Antagonistic Center Surround
Özcan Urhan (CSEM / ETH Zurich), Arturo di Girolamo, Christian Metzner
This paper presents a novel dual-line dynamic vision sensor (DVS) integrating a configurable antagonistic center-surround network. Inspired by biological retina processing, the sensor combines spatial and temporal filtering to suppress redundant or uninformative signals such as global lighting fluctuations. With a >120 dB dynamic range, sub-250 mW power, and 12 μs latency, it is well-suited for fast, data-efficient machine vision tasks in industrial environments.
A DC-Coupled Neural Recording Analog Front-End with Bi-Level Bulk Modulation-Based EDO Compensation in 40nm Bulk CMOS
Arnau Diez-Clos (CSEM / TU Delft), Xiaohua Huang, Bert Monna, Dante G. Muratore
This work introduces a compact, low-noise analog front-end (AFE) for neural recording applications. To deal with electrode DC offsets without large passive components or high-resolution digital loops, the design uses a bi-level bulk modulation scheme embedded in the input stage. Implemented in 40nm CMOS, the AFE achieves 1.69 µVrms input-referred noise in the 1–500 Hz band, 2.48 µW power consumption, and occupies only 0.0028 mm² per channel—key metrics for scalable high-density brain–machine interfaces.
A High-PSRR and Low-Noise CMOS-Based Reference with Barrel Shifting and Notch Filtering
Amrith Sukumaran, Enrico Miotello, Chun-Min Zhang, Francesco Caruso, Paula Blanca Cruz, Stéphane Emery (CSEM)
This paper proposes a fully integrated voltage reference generator that operates from 0.7 V and achieves strong resilience against supply noise. The design combines a 3-phase barrel-shifting current mirror with a dual-stage switched-capacitor notch filter to suppress low-frequency flicker noise and ripple, reaching −95 dB PSRR at 50 Hz. It achieves a temperature drift of 30 ppm/°C and 19.7 µVrms integrated noise within a 0.01 mm² area in a 22nm FDSOI process.
Together, these contributions address key challenges in sensing, conditioning, and referencing for integrated systems operating under constrained power, area, and signal integrity requirements. They also highlight the diversity and quality of research enabled through the SwissChips program and CSEM’s collaboration with academic partners.
