Chip Design
The SwissChips chip gallery highlights our latest chip designs including those from our SwissChips research and externally supported chip designs through our IC Design application process (under WP1).
📊 SwissChips Chip Design Statistics:
Year 1 (as of July 2025):
Internal chips designed: 34
External chip designs, proposals accepted: 7
More about our application process for IC design support for research and teaching projects at Swiss universities and universities of applied sciences can be found here: WP1 IC Design
SwissChips Chip Design Gallery
Mothra, ASIC, 2025 (IIP, ETH Zurich)
Ankara, PLL-XO co-design, 2025 (EECIS, ETH Zurich)
Deltasense, Bio-signal ADC, 2025 (EECIS, ETH Zurich)
Basilisk, 2024 (PULP Platform, ETH Zurich)
Astral, 2024 (PULP Platform, ETH Zurich)
Koopa, 2025 (PULP Platform)
Chip-4Dopamine, 2025 (BCI Lab, EPFL)
Chip-4Brain, 2025 (BCI Lab, EPFL)
Zervreilahorn, application-specific integrated circuit, OST, 2025 (externally supported chip through SwissChips WP1: IC design support)
M-FLOCC, 2025 (Lab of Wave Engineering, EPFL)
Chip Details
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Mothra, ASIC, 2025 (IIP, ETH Zurich) -
Ankara, PLL-XO co-design, 2025 (EECIS, ETH Zurich) -
Deltasense, Bio-signal ADC, 2025 (EECIS, ETH Zurich) -
Basilisk, 2024 (PULP Platform, ETH Zurich) -
Astral, 2024 (PULP Platform, ETH Zurich) -
Koopa, 2025 (PULP Platform) -
Chip-4Dopamine, 2025 (BCI Lab, EPFL) -
Chip-4Brain, 2025 (BCI Lab, EPFL) -
Zervreilahorn, application-specific integrated circuit, 2025 (OST) -
M-FLOCC, 2025 (Lab of Wave Engineering, EPFL)